Data is presently transferred between circuits using data signals and a separate clock signal, as illustrated in FIG. 1. During the transfer, the data signal 10 applied to the data bus line must remain valid for a predefined period before and after a transition 13 of the clock signal 12, at the destination of the data transfer. The clock signal transition 13 informs the receiving memory device to read the transferred data 1 during this period of signal validity 14. The required period of data validity before the clock signal transition 13 is referred to as the setup time tsetup and the required period of data validity after the clock signal transition 3 is referred to as the hold time thold.
Generally, to increase the performance of integrated circuits, it is necessary to increase the clock rate and the density of the integrated circuitry. The increased performance of integrated circuits creates several problems with the traditional means of data transfer. The increased clock rate is associated with an increased data transfer rate and this increased data transfer rate necessarily reduces both the setup and hold times. A reduced period of data validity makes it increasingly difficult to synchronize the transition of the clock signal with the setup and hold times at the destination device. The increasing density of integrated circuitry requires the use of smaller circuit traces that have a higher resistance than do larger traces. This increased resistance creates greater propagation delays in the transfer of data and clock signals between the source and destinations devices. These delays may vary depending upon the layout, size, and length of the traces connecting the source and destination devices. Because The propagation delay of one line may be different from another line, a signal generated on one line may take longer to travel to its destination than a simultaneously generated signal on another line. This variable delay time, makes it difficult to use a global clock signal to synchronize all of the data transfers on a printed circuit board or a chip with multiple circuits or on integrated circuit. Delays incurred by the clock signal may not be identical to the delays incurred by data signals, making it difficult to synchronize the clock signal transition with the setup and hold times at the destination device. The electrical properties of integrated circuit materials change with changes in temperature. These changing properties create variations in the signal delays that compound the difficulty of synchronizing clock and data signals over the range of operating temperatures for a circuit.
Presently, the above-described problems can be addressed. The propagation delays for the data and clock signals may be made nearly identical by collocating the source and destination points for these signals and routing the signal traces along nearly identical paths. Alternatively, an iterative process of modeling the performance of the integrated circuit and incrementally adjusting the signal routing may be used to achieve the desired synchronization between the data and clock signals.
Solutions are difficult and expensive to implement. Neither solution is desirable and neither solution reduces the effect of the above-described problems as the clock rate and circuit densities are increased.